Jan 11, 2007
Nanoscale switches can improve CMOS circuits
As the scaling of CMOS electronics to ever-smaller sizes continues, it is becoming increasingly difficult to realize performance improvements other than increased density. Complementing CMOS with new nanoscale switching devices can result in reduced power, higher clock speeds and high defect tolerance for some types of circuits.
Now that CMOS feature sizes are approaching the 50 nm scale, a large number of problems are confronting the industry. The expense of fabricating chips is rising dramatically with the demands of increasing manufacturing tolerances, and the chips that are being produced have severe constraints in terms of operating frequency and power dissipation.
In our present work at HP Labs, we have followed up on an interesting proposal by Strukov and Likharev at the University of Stony Brook to investigate in detail a new architecture that combines a nanowire and switch fabric interfaced to a CMOS substrate that has properties similar to those of a field programmable gate array (FPGA). We describe a system that should be manufacturable using currently available technology that can increase the usable device density by a factor of eight, increase the clock speed by a factor of two and potentially decrease the power dissipation compared with FPGAs built using the same CMOS technology.
This is an example of a more comprehensive strategy for improving the efficiency of existing semiconductor technology: placing a level of intelligence and configurability in the interconnect can have a profound effect on integrated circuit performance, and can be used to extend Moore's Law significantly without having to shrink the transistors.
About the author
Greg Snider is currently a senior architect in the Quantum Science Research Group at Hewlett-Packard Labs in Palo Alto, CA.