Boolean logic-based computation is currently the dominant paradigm; so much research has focused on mitigating crumminess for nanoscale logic. Many proposals have been made: crossbars of configurable nanodevices; defect detection and avoidance; massive redundancy; applications of coding theory to logic circuit design; self-checking circuitry; hybrid analog/digital structures; and so on. But power dissipation, reliability, processing speed and manufacturing scalability remain significant challenges.

Alternatively, one can stop fighting inherent nanodevice behavior and instead try to exploit it. We are investigating combining simple, regular structures of dynamical nanodevices with conventional CMOS to create self-organizing, recurrent networks capable of massive parallelism. Our simulations show that such networks are quite insensitive to device variability and high defect-rates, thus enabling low-cost manufacturing. In principle, they could be much simpler to program, since the self-organization paradigm more closely resembles "training" than compilation or configuration.

We are currently refining the physical models of our nanodevices so that we can better engineer their properties and we plan to implement such networks in a hybrid of CMOS and nano-crossbars. The approach is complementary to, not competitive with, conventional logic-based computation. We are investigating it as a basis for probabilistic computing – dealing with uncertainty and adapting to change in a dynamic world. Applications include decision-making, pattern recognition and robotics.