Since defects will be the nature property of the nanoscale electronic devices as the critical dimensions of the devices are scaling down to molecular size, further improvement of the defect rates will be extremely costly from an economic point of view and will soon hit the physical limit. In order to cope with the defects, one can use a software approach by mapping out defects and reconfiguring the circuits for low-density defects. But for high-density devices with more defects, the software approach will be prohibitive in terms of the overhead and complexity for mapping and reconfiguration. A build-in hardware design to tolerate the defects in the nano devices will be highly desired.

As an experimental demonstration of such a design, we have built a 50 nm half-pitch nanocrossbar circuit using imprint lithography and configured it for a demux application. Utilizing a class of Hamming codes in the hardware design, we experimentally demonstrated defect-tolerant demux operations on a 12 × 8 nanocrossbar array with up to two stuck-open defects per addressed line, i.e. ~15% defect rate.

The scheme as demonstrated in this work can be applied to large scale ultra-dense electronic circuits, such as memory and logic, as well as high-density nanowire sensory circuits.