For large-scale fabrication of CNT-FETs to become possible, CNTs need to be placed at selected positions of the circuit with high yield and each CNT-FET needs to be addressed individually with its own local gate. The assembly also needs to be carried out in an environment that does not damage other components in the circuit.
Dielectrophoretic (DEP) assembly of CNTs is promising as it offers a quick and convenient method to assemble CNTs from solution.
In the past, DEP assembled CNT-FET devices only used a global back gate, which gives rise to poor device performance as well as not being able to address each CNT-FET individually. In a paper published in Nanotechnology, Stokes and Khondaker reported a technique of fabricating high-performance DEP assembled CNT-FETs that can also be addressed individually.
In this study, source and drain electrodes with scalable local gates were patterned followed by assembly of CNTs from solution by applying a non-uniform electric field. Solution processibility has several advantages by limiting the cost and covering large areas, which allows for CMOS compatibility, as it does not require high-temperature growth of CNTs directly on the circuit. On-off ratios of more than 10,000 and sub-threshold swings of 170 mV/decade were observed. High-performance FET devices demonstrated in this study may be due to channel control operation in contrast to contact control operation as in a back gated geometry.
This is a major step towards mass production of nanoelectronic devices using CNTs. However, more work will be needed to decrease contact resistance of the DEP assembled devices and scaling down the gate width for even better device performance. The Khondaker group is currently working towards achieving these goals.