In terms of technology, combining fabrication processes of nanomechanical resonators with a standard CMOS technology is challenging, the limiting factor being mainly lithography. In this sense, the general trend of miniaturizing devices to the submicron scale has created new needs: cheaper, parallel and if possible “clean” (resistless) nanopatterning techniques are nowadays highly needed. In a paper recently published in Nanotechnology, a novel wafer-scale technological process based on post-processing CMOS circuits using nanostencil lithography (nSL) is presented. nSL is a high-resolution, clean and parallel shadow-mask technique that directly deposits a controlled amount of material on a surface by evaporation through apertures made in a thin membrane.

The paper demonstrates the simultaneous patterning by nSL of thousands of silicon nano/micromechanical resonators by post-processing standard CMOS substrates using one single metal evaporation through a shadow-mask (nSL), pattern transfer to silicon and subsequent etch of the sacrificial layer. The electrical characterization of the fabricated NEMS/CMOS resonators confirms the improvement provided by the monolithic integration.

As proof-of-concept towards an application as high-performance sensors, NEMS/CMOS resonators are successfully implemented as ultra-sensitive areal mass sensors: nanocantilevers resonators placed in a high-vacuum evaporation chamber are used to monitor in situ the deposition of sub-nanometer thick gold layers. The principle of the measurement is to monitor the decrease of resonance frequency induced by the mass loading on top of the resonator. The demonstrated sensitivity is orders of magnitude better than classical and commercially available quartz-crystal microbalances.