However, there are several major hurdles that need to be overcome before CNTs can claim superiority over standard, well established silicon technology. One of them is the lack of process technology capable of developing reliable and reproducible CNTs on the wafer scale and precise growth control.

Scientists from the University of Cambridge (CAPE- High Voltage Microelectronics) and University of Warwick (Sensors Research Laboratory) are keen to integrate/develop CNTs on fully processed CMOS wafers; gaining the benefits of both CNTs and on-chip electronics. However, growing nanomaterials on a fully processed CMOS wafer is challenging because of several constraints (for example, thermal budget) imposed by the CMOS technology.

Reporting their results in the journal Nanotechnology, they have proposed a new concept to grow spaghetti-like CNTs at addressable areas on a fully processed CMOS substrate – without hampering on-chip electronics. A standard SOI CMOS process was used to fabricate the basic gas sensor (which incorporated a high-temperature tungsten micro-heater and interdigitated electrodes) and on-chip circuitry from a commercial foundry.

The dielectric membrane (formed by post CMOS DRIE processing) reduces the power consumption for a given operating temperature (for example, 500 °C), while providing isolation from the electronic circuits adjacent to the membrane.

CNTs were grown successfully on gold interdigitated electrodes with the tungsten micro-heater at a temperature of 725 °C. This technique was extended to grow CNTs on more than one device to show the concept of wafer-level growth by powering several micro-heaters simultaneously.

The groups have also been developing novel processes for growing other nanomaterials such as ZnO nanowires and WO3 nanorods on CMOS substrates without hampering the performance of on-chip electronics.

More information on this technique can be found in the journal Nanotechnology.