Feb 15, 2011
Formation of Kirkendall voids in silicon nanowire contacts
High-performance nanowire devices require reliable, low-resistance contacts. After depositing metal contacts on semiconductor nanowires, the structure can be annealed to reduce its contact resistance. Annealing facilitates metal-semiconductor interdiffusion and the formation of desirable phases, but this needs to be monitored. Traditional phase identification techniques such as X-ray diffraction and Auger depth profiling are not effective due to the small volume of the metal-nanowire contact region. So, how do we discover what's actually going on right at the nanowire-metal contact region?
Researchers in the US have successfully imaged the evolution of Ti/Al/Ti/Au source/drain contacts on silicon nanowire transistors annealed at different temperatures. Using a focused ion-beam tool, the scientists cut thin slices of the contact region within these nanotransistors, lifted them up and looked at them in a scanning transmission electron microscope. What the team found was unexpected.
In planar devices, titanium and other contact metals react with silicon upon heat-treatment and form metal silicides, which are essential for low-resistance contacts. However, in the case of silicon nanowire 3D geometry, the silicon actually diffused out of the nanowire into the metal contact layer leaving a void behind. This type of voiding is often observed in planar geometry diffusion couples and is called a "Kirkendall void".
When it comes to annealing silicon nanowire contacts, the researchers discovered that there is a "sweet spot" between forming the right amount of low-resistance phases and destroying the device due to Kirkendall voiding. At 750 °C the heat-treatment "emptied" almost half of the nanowire under the contact and still produced favorable contact properties, whereas the 850 °C anneal completely consumed the nanowire and resulted in device failure (see images above). This is the first observation of Kirkendall void formation in nanowire devices, and its role in the device performance. This study highlights the need for designing metal contacts specifically for nanoscale devices, keeping in mind their three-dimensional structure.
The team plans to investigate other metallization combinations on a variety of semiconductor nanowires using the same techniques, and to correlate the contact microstructures with device performance. Such information will be extremely useful for researchers working with silicon and other nanowire devices. One can imagine using this nanoscale voiding process to make nanochannels, which could be potentially used in biosensors.
The researchers presented their work in the journal Nanotechnology.
About the author
Dr Abhishek Motayed is an assistant research scientist at the University of Maryland, US, and a guest researcher at the National Institute of Standards and Technology (NIST), Gaithersburg, US.