While the aggressive downscaling leading to the evolution of MOSFET architectures have preferred the development of symmetric self-aligned technology, some imperfections in devices are bound to exist. One such ‘traditional’ imperfection is the misalignment between front and back gates. This reported work demonstrates that transforming a detrimental feature into a unique positive attribute without significantly degrading other performance metrics is an innovative way forward to harness the energy efficient operation at lower applied voltages in the nanoscale regime.

The most distinguishing feature of the work is the enhanced degree of impact ionization achieved through an inclined conduction channel facilitated by gate misalignment which improves the product of current density and electric field, a crucial parameter governing the degree of impact ionization. Misalignment results in a redistribution of generated electrons and holes in the semiconductor film at nearly sub-bandgap voltages. This also facilitates a localized minimal depletion region, which is sufficient to turn-off the device in off-state, while maintaining a higher value of current density to aid impact ionization and trigger the steep switching. The proposed methodology can even be applied to Germanium junctionless transistors, which despite their lower bandgap and being more susceptible to band-to-band tunnelling, achieve nearly 3 orders of sharp increase in the drain current with an ideal subthreshold swing lower than 1 mV/decade.

The research work is supported by Council of Scientific and Industrial Research, Government of India, and University Grants Commission, Government of India, through Junior Research Fellowship award to Manish Gupta.

More information about this research can be found in the journal Nanotechnology 27 455204