"Our result is pretty amazing because the techniques to make the field-effect transistors have not been optimized or refined as those for commercial flash memories have," team leader Päivi Törmä told nanotechweb.org.

Another interesting finding in the work is that the nanotube memories are durable – they can operate for more than 104 cycles, a figure that is often the lifetime specified for flash memories.

Layering up

Törmä and colleagues made the single-walled carbon nanotube field-effect transistor (CNT-FET) memory elements by first growing a HfO2 layer using atomic layer deposition (in collaboration with the company Beneq Oy, Finland) on top of a highly doped silicon wafer that also acts as a back gate. Next, the researchers dispersed nanotubes onto the HfO2 from a suspension and precisely placed the tubes in a predefined alignment marker matrix with the help of an atomic force microscope. Suitable nanotubes were then contacted with palladium electrodes using e-beam lithography. Finally, another layer of HfO2 was deposited on top of the devices as a passivation layer to reduce surface effects.

"The observed operation speed is most likely due to the combined properties of the carbon nanotubes and the HfO2 dielectric," explained Törmä. The electrical properties of carbon nanotubes are well suited for high-speed operation and the nanotubes are very sensitive to the surrounding electrical environment, she adds. The HfO2 gate dielectric contains defect states that are situated above, but close in energy to the CNT bandgap. These defect states can be efficiently charged and discharged with the charge carriers in the nanotubes.

The devices might find use in flash memory hard drives but are best suited to portable devices, such as mobile phones, laptops, PDAs and USB memory drives, because these applications require extremely low operation voltages and feature small leakage currents. And being nanoscale, the devices can also be densely packed in a given area.

The current structure is not yet suitable for mass production because global gates are employed, but this problem can be overcome by using a local gate structure. This would also make fabricating the devices compatible with conventional silicon electronics manufacture.

There are other challenges to overcome too: the precise electrical properties of CNTs and their positioning on a chip need to better controlled.

"Because the speed of the devices is probably limited by our measurement set up, we would like to investigate the intrinsic speed limitation of the nanotube memories," said Törmä. "For that, we need to optimize their design and our measurement – to reduce parasitic capacitances and to accommodate higher frequencies."

The work was reported in Nano Letters.