Jun 4, 2009
Graphene-on-SiC FETs near DARPA targets
HRL Laboratories has claimed a big leap forward in radio-frequency graphene transistors just days after describing the first such devices in IEEE Electron Device Letters.
On May 21, the Malibu, California, research institution said that it had made devices from single-layer graphene on 2 inch diameter SiC wafers with much-improved performance figures.
“They have world-record field mobility of approximately 6000 cm2/Vs, which is six to eight times higher than current state-of-the-art silicon n-MOSFETs,” said HRL senior scientist Jeong-Sun Moon.
The researcher also described the ratio of on-state current to off-state leakage current, Ion/Ioff of 19 for the devices as “excellent”.
In comparison, the first graphene RF field-effect transistors that HRL worked on achieved just 200 cm2/Vs field mobility and Ion/Ioff of 3–4.
Details of these pioneering 2 µm gate-length devices, produced under the US Carbon Electronics for RF Applications program, or CERA, were revealed online on May 12.
Originally announced in December 2008, the current-gain cut-off frequency fT for the first transistors was 4.4 GHz.
This DARPA-funded CERA work, performed by HRL and the US Naval Research Laboratory, seeks to exploit graphene for high-bandwidth communications, imaging and radar systems.
For the original devices, the team produced the graphene by evaporating silicon from 6H crystal polytype SiC at around 1600 °C and less than 10–4 mbar. They did this using an Aixtron VP508 CVD reactor “because it has excellent temperature uniformity”.
As a result, the surface of the 2 inch diameter wafer was covered in the single sheet of hexagonally arranged carbon atoms that constitutes graphene. However, a second graphene layer was also present on top of this across much of the wafer.
The transistors were made using a standard photoresist process and oxygen reactive ion etching. Source and drain contacts were fabricated from an unalloyed combination of titanium, platinum and gold.
The team produced a 20 nm thick alumina gate dielectric using atomic layer deposition, but writes that this might actually have restricted device performance due to trapped interface charges.
Now that some initial limitations have been overcome, Jeong-Sun Moon is confident that the technology can go on and meet the CERA phase I goal of delivering Hall mobility above 10,000 cm2/Vs.
“The results and rate of progress validate our technical approach,” he said.