The feature sizes in conventional microelectronic circuits are getting ever smaller and could reach the limit imposed by the fundamental properties of silicon in the near future. Carbon nanotubes – rolled up sheets of graphite – are ideal alternatives for electronics applications, such as integrated circuits, flexible displays and solar cells, thanks to their high electrical conductivity and toughness. However, it is still difficult to produce networks of uniformly dense nanotubes that are aligned over large areas.

Now, a team led by Zhenan Bao reports on a new way to controllably deposit SWNT network thin-film transistors (TFTs) from solution over areas as large as 6 inches. The samples are made by spin-coating a purified, but unsorted solution of SWNTs.

"Because all the processing is performed at room temperature, the new technique is perfectly compatible with integrating the resulting transistor networks onto plastic, flexible substrates," team member Melburne LeMieux told nanotechweb.org.

The SWCNT TFTs have on/off ratios averaging more than 105 and charge mobilities of 2 cm2/Vs, and this without any pre-or post-processing steps. The spin-assembly technique employed produces tunable density arrays of nanotubes that are highly aligned in one direction. This, combined with selective surface chemistry, results in networks of semiconducting nanotubes that make excellent TFTs – something that the researchers confirmed with Raman spectroscopy and electrical testing.

Spurred on by these results, the team will now try to understand how different chemical groups on the substrate underneath the carbon nanotubes affect charge transport within the network. "This will hopefully provide another route to better tune the electronic properties of these materials and provide more fundamental insights into their charge transport properties," said LeMieux.

The researchers reported their work in ACS Nano.