Jan 21, 2010
InAs nanowires get p-doped
Researchers at the University of California have developed a new method to p-dope as-grown semiconductor nanowires – something that has been difficult to do until now. The technique could be used to make high-speed diodes and low-power transistors based on InAs and other III-V nanostructures that are not compatible with conventional ion-implantation processes.
Although researchers have already reported on techniques such as in situ doping during semiconductor nanowire growth, post-growth patterned doping should be better for most fabrication schemes, says team leader Ali Javey. However, such doping is particularly difficult in nanowire systems where conventional ion-implantation techniques often cause severe lattice damage that results in high leakage currents.
One very promising semiconductor for nanowires is indium arsenide (InAs) because electrons travel through the material at high speeds, which makes for good electrical conductivity. It can also be easily contacted to metal electrodes, making device fabrication easy. However, p-doping InAs has always been a challenge due to the Fermi-level pinning that occurs at the InAs surface, which results in an electron-rich surface layer. Javey's team has now overcome this problem with its patterned surface doping approach to produce p-doped regions.
The researchers began by making InAs nanowire gated diodes and p-MOSFETs by combining photolithographic techniques with a simple zinc gas phase surface technique, also developed by the Berkeley team. The gated diodes produced have ideality factors of around 1.5, which indicates high-quality p-n junctions, and the p-MOSFETs have on-off current ratios of more than 103, which shows how versatile the patterned doping technique is for making various high-performance devices. "This is the first time that a InAs-based p-MOSFET with heavily doped contacts has been demonstrated," Javey told nanotechweb.org.
The technique could be ideal for making high-speed diodes and low-power transistors based on InAs nanostructures, he adds.
The scientists now plan to further investigate the performance limits of the InAs nanoscale devices made using their technique. They also hope to extend their approach to other III-V semiconductors.
The work was reported in Nano Letters.
About the author
Belle Dumé is contributing editor at nanotechweb.org