Nov 4, 2010
Constricting nanodevices for digital applications
Researchers in the US have developed a new way to pattern monolayer graphene “nanoconstriction” field-effect transistors (NCFETs) that are smaller than 10 nm. The devices have room temperature current on/off ratios of larger than 1000, a level that is high enough for applications in advanced digital electronics.
Graphene, a layer of carbon atoms arranged in a honeycombed lattice, is extremely promising for use in new generation digital electronics devices thanks to the fact that electrons move through the material at extremely high speeds. However, graphene in its bulk state (around 2 µm in size) does suffer from the fact that it is a "zero-gap" semiconductor, that is, it lacks an energy gap. This means that it cannot be used in digital applications. An energy gap can be created through quantum confinement – for example, by making graphene nanoribbons smaller than 2 nm across, but such a feat is impossible with state-of-the-art lithographic techniques that are limited to a resolution of 10–20 nm.
A T Charlie Johnson of the University of Pennsylvania and colleagues in Kentucky and Swarthmore may now have come up with a solution to this challenge.
The researchers began by patterning bow-tie-shaped gold nanowires atop monolayer graphene sheets using conventional lithography. Next, they patterned larger palladium pads to make electrical contacts to the nanowires. They then used a computer-controlled "feedback electromigration" technique to further narrow the gold nanowires and form tiny constrictions in the “knot” of the bow-tie structures.
The beauty of the technique is that the narrowed gold structure acts as an etch mask for an oxygen plasma step that etches away graphene not protected by the mask. The gold etchant can then also be used to remove any remaining gold on top of the graphene, so leaving a patterned graphene nanoconstriction contacted by palladium source/drain electrodes.
Johnson's team fabricated the transistors on an oxidized, highly P++ doped silicon wafer that is around 300 nm thick, where the bulk of the silicon wafer may be used as a back gate. By tuning the gate voltage applied to the doped silicon, the researchers were able to switch the conductance of the NCFET on and off.
“The conductance on/off ratio of our graphene NCFETs becomes larger as we narrow the constriction further, reaching values larger than 1000 at room temperature for constrictions widths below 10 nm,” Johnson told nanotechweb.org. “Since the palladium contacts are large area (spread across several square microns), the contact resistance is negligible in our devices. This means that the measured conductance is characteristic of the graphene nanoconstriction, with a minimum contribution from the contacts.”
Graphene transistors with current on/off ratios greater than 1000 could be suitable for digital electronics applications say the researchers, who now hope to increase the efficiency of their top-down fabrication process to produce integrated circuits containing NCFETs. “We have already simultaneously fabricated multiple NCFETs on the same piece of exfoliated graphene,” explained Johnson, “and refining our technique further might allow us to pattern circuits with many transistors with high on/off ratios on large-area CVD graphene”.
Ideally, the researchers would to like to control the precise atomic structure of the NCFETs since it controls the final properties of the transistors, such as their energy gap and current on/off ratio. “Measuring the electronic properties of the NCFETs as the temperature changes will also allow us to better understand the physics behind their electronic behaviour,” added Johnson.
The work will shortly be published in Small. It can currently be seen on arXiv.
About the author
Belle Dumé is contributing editor at nanotechweb.org