Conventional microelectronic circuits are getting ever smaller and could reach the limit imposed by the fundamental properties of silicon as early as the end of this decade. Researchers are thus looking into high-performance alternatives, such as compound III-V semiconductors, while respecting conventional and well established processing methods that involve silicon substrates. Although schemes to epitaxially grow these compounds directly onto silicon wafers exist, the challenge here is that silicon and III-V semiconductors often have very large lattice mismatches. This makes it extremely difficult to grow high-quality single-crystalline layers needed for device components.

The new approach, developed by Ali Javey and colleagues overcomes this problem. As a proof of concept, the researchers focused on indium arsenide (InAs), a compound semiconductor that has a high conductivity and a material in which electrons move very fast.

XOI
By using an epitaxial layer transfer technique, Javey and co-workers place ultrathin layers of InAs, just a few atomic layers thick, on silicon/silica substrates. The structures look like conventional silicon-on-insulator (SOI) structures except that the top layer is InAs rather than silicon. "We call this platform X on insulator, or XOI, where X stands for any predefined material system," explained Javey.

InAs is a good choice for such studies but it does suffer from the fact that it has a small bandgap, which makes it less than ideal for electronics. By making the X layer just a few nanometres thick though, the Berkeley scientists have been able to drastically reduce leakage currents, and so achieve higher performance in devices made from this material. Indeed, a finished transistor was able to operate at just 0.5 V and had an on/off current ratio of more than 10,000.

The InAs XOI transistors with a channel length of around 500 nm also have a transconductance of about 1.6 mS/µm at 0.5 V. In contrast silicon MOSFETs with similar channel lengths deliver a transconductance of only 0.2 mS/µm at a much higher operating voltage of around 3.3 V.

The technique is a viable route for making high-performance III-V transistors using conventional silicon processing, where the silicon substrates are still used for handling and processing, says Javey. The only difference is that an ultrathin III-V layer on top now acts as the active device layer. "What's more, our XOI structures have clean interfaces thanks to the thermally grown InAs that we purposely form to act as a passivation layer," he told nanotechweb.org. "This also helps us to produce higher-performance transistors."

The team now plans to examine the performance limits of its XOI transistors by fabricating ultrashort channel devices. "We would also like to develop the wafer-bonding equivalent of our process," revealed Javey.

The work was published in Nature.