Jul 20, 2012
III-V semiconductors grow on silicon
Researchers at the University of California at Berkeley have made the first III-V complementary metal-oxide-semiconductor (CMOS) circuits on a silicon-handling wafer. The work is an important step towards using III-V semiconductors in future electronics they say.
Conventional microelectronic circuits, based on metal-oxide-semiconductor field-effect transistors (MOSFETs) have become increasingly smaller with time, and this is one of the main reasons for their success. However, these transistors might reach the size limit imposed by the fundamental properties of silicon in the next few years. Researchers are thus studying high-performance transistors based on alternative channel materials such as compound III-V semiconductors, but these materials need to be processed using conventional, well established techniques that involve commercial silicon substrates.
III-V semiconductors can be grown directly onto silicon wafers but this is not easy because optimal p- and n-type III-V compounds have very different lattice parameters to each other, and to silicon. This means that high-quality single-crystalline layers needed for device components are currently impossible to grow using such a technique.
A new method developed by Ali Javey and colleagues that involves using III-Vs grown on insulators using an epitaxial layer transfer process overcomes this problem.
The team transfer ultrathin layers of indium arsenide (for n-type FETs) and indium gallium antimonide (for p-type FETs) from their original growth substrates onto silicon wafers using a two-step process. The structures produced are similar to conventional silicon-on-insulator (SOI) structures except that the top, active, layer is the single-crystal III-V film rather than silicon. The researchers have already made such a platform before, dubbed X on insulator, or XOI.
“We can also realize this structure by conventional wafer bonding processes,” explained Javey, “but the main point is that the epitaxial transfer technique eliminates the lattice mismatch between any III-V semiconductors and silicon, and therefore allows for high carrier motilities in both n- and p-type devices.”
The peak effective mobilities of the complementary devices were measured to be around 1190 and 370 cm2/(V s) for electrons and holes, respectively, both of which are higher than the corresponding values in state-of-the-art silicon MOSFETs. The researchers also showed that they could perform III-V CMOS logic operations for the first time using such structures by fabricating NOT and NAND gates on the XOI platforms.
The technique could be a good way to make high-performance III-V transistors using conventional silicon processing, says Javey. “In the future, we shall also need to explore 3D assembly of III-V XOI materials to come up with a more practical technique to fabricate a high density of devices on the same chip.”
The current work is detailed in Nano Letters.
About the author
Belle Dumé is contributing editor at nanotechweb.org.