Aug 2, 2012
Nanowires give vertical transistors a boost
Gate structures in silicon-based transistors will have to evolve in the future as these devices become ever smaller. Researchers in Japan have made an important advance in developing these next-generation architectures by successfully fabricating vertical transistors from semiconducting nanowires on a silicon substrate. The wires, made from indium gallium arsenide, are surrounded by 3D – rather than planar-shaped – gates and the finished devices have extremely good electronic properties.
Conventional microelectronic circuits, based on metal-oxide-semiconductor field-effect transistors (MOSFETs) have become increasingly smaller with time and this is one of the main reasons for their success. However, many problems, such as off-state current leakage and the so-called short-channel effect, become more apparent as device size decreases.
To overcome these complications, the gate structure of silicon-based transistors has already gone from being 2D (planar) to 3D with the development of "fin" field-effect transistors in the last few years. Researchers are currently looking at planar and fin architectures using compound III-V semiconductors, like InGaAs, as alternatives to complementary metal-oxide-semiconductors (CMOS) because of their high electron mobility and excellent compatibility with existing gate-dielectric materials. However, a new "surrounding-gate" architecture – where the gate is wrapped around a nanowire channel – also appears to show great promise. Such structures are difficult to study though because it is not easy to integrate freestanding semiconducting nanostructures, like nanowires, onto silicon substrates.
Katsuhiro Tomioka and colleagues at Hokkaido University in Sapporo are now reporting on a new technique to grow vertical InGaAs nanowires and show that they can fabricate surrounding-gate transistors using these wires and core-multishell nanowires (made from InGaAs/InP/InAlAs/InGaAs) as channels. The channels have a six-sided structure, which has the benefit of greatly increasing on-state current and device transconductance.
The researchers, who report their work in Nature, measured the on-off current ratio in their devices to be around 108 – a value that is superior to those observed in devices made from similar materials with equivalent dimensions. The estimated field-effect mobility of around 7850 cm2/V· s of the transistors also appears to be much higher than the typical electron mobility of a Si metal-oxide-semiconductor FET. These properties mean that the new devices could be useful as building blocks for high-speed wireless networks and other sophisticated technologies, said Tomioka.
"Nature recently published several review papers about new gate architectures, alternative channels and alternative switching mechanisms for future CMOS technologies," he explained. "At a recent major conference for transistor researchers, Intel suggested that integrating group III–V material onto silicon could be the future of low-power, high-speed CMOS. The company also emphasised the importance of vertically oriented 3D transistors.
"Our results are the first to realize these predictions," he told nanotechweb.org.
The Japan researchers have also already made "steep-subthreshold slope" tunnel FETs using their technique – a feat that "goes far beyond" what was outlined in the Nature reviews and at the conference, they said.
The team now plans to fabricate p-type FETs for logic operations using its technique.
About the author
Belle Dumé is contributing editor at nanotechweb.org.