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Right-click to download interview with Adam Micolich (12.8 MB MP3)

"What’s nice about the horizontal orientation is if you have two gates or four gates it’s exactly the same process, so having more gates doesn’t get any harder," says Adam Micolich from the University of South Wales in Australia. "We can then tweak that further and start to make simple circuits with multiple transistors in."

Micolich turned his attention to the horizontal architecture following a sabbatical at Lund University, Sweden, where Lars Samuelson’s group were working on these orientations. While industry has been focused on vertical nanowires, Micolich says that for research the horizontal orientation can be more convenient. As it turns out, the horizontal orientation also has several advantages for simplifying production.

"If you want more than one gate, you can set them side by side and since you’re writing your patterns from above, writing more features adjacent to each other is not very hard," says Micolich. "In the vertical orientation if you want to add more gates you have to structure in the vertical direction and that means you have to put a whole pile of different layers in there to get the control."

Further down the line this work may be useful for 3D networks of nanowire transistors. These would maximise the use of space on the chip – termed "real estate" in the industry - by building transistor architectures in all three directions. "You can imagine if you are just building little houses you run out of space quickly but if you build giant apartment complexes you can fit more people in the same real estate area," says Micolich. Moving to this kind of nanoscale transistor metropolis is still a long way in the future, but would require advances in fabrication procedures in both the horizontal and vertical orientations.

Gate transistor wrapping

One of the challenges as the size of electronics decreases is the consequent reduction in area for coupling gates to transistor channels. Scientists have tried various approaches to boost this area by folding gates around channel surfaces. The all-around wrap-gate used by Micolich and colleagues in Australia and Sweden takes this one step further.

"It’s something that these nanowires allow you to do very well," says Micolich. "You grow this fine needle-like structure and put metal all around it, and then you can knock it over and you essentially have a channel running along a surface with a gate wrapped all around."

"Gate-all-around (or wrap-gate) transistor structures offer optimal electrostatic control of the transistor channel and is the direction the semiconductor industry is shifting into," says Wei Lu of the University of Michigan, who was not involved with the current research. "In this work, Burke, Micolich and colleagues showed that multiple wrap-gates can be fabricated along a single InAs nanowire with little crosstalk between the gates. By using a horizontal structure, the authors simplify the fabrication complexity so that fabrication of additional gates requires no additional cost. This work is certainly interesting, if the goal is to build a functional circuit along a single nanowire."

Ugly ducklings?

Micolich and his colleagues were keen to improve the quality of the devices they fabricated, as well as the quantity. This turned out to be tricky as the materials they used are inevitably granular at a scale comparable with the device features, thwarting attempts to replicate the clean lines and layers in their schematic designs. Lead author Adam Burke, who completed the majority of the experimental work, found that the visible imperfections did not affect the structures as much as you might expect.

"There’s an almost famous saying that goes: ‘usually the devices you get the best data from are the ones that look the ugliest’," says Micolich. "They’re kind of defect-tolerant in a way." The researchers suggest that this may be because the holes visible under a microscope do not penetrate all the way through to the next layer. Scale may also be a factor, as defects that seem large in relation to the device are still only nanometres in size, which may mitigate their impact.

Full details of their research are reported in Nano Letters 10.1021/nl5043243.

For some of the latest developments in other aspects of nanoelectronics visit the Nanotechnology special issue on paper electronics.