TFETs could be better than conventional CMOS planar transistors that have been scaled down. For one, they have lower leakage currents, which can slow down ON-OFF switching speeds. Recently, researchers also found that heterostructure tunnel junctions in so-called non-planar gate-all-around nanowire (GAA NW) TFETs have a higher tunnel current than transistors made from only silicon. However, the overall performance and power consumption of these transistors is not yet good enough for mobile applications.

Now, a team of researchers led by Muhammad Hussain of the Integrated Nanotechnology Lab at KAUST have made a TFET based on nanotubes that works using very little power but which has a much higher drive current than GAA NW TFETs.

"Unique architecture"

Hussain says that the new TFETs are better thanks to their unique architecture, which consists of core (inner) and shell (outer) gates for nanotube heterostructures made of silicon/indium arsenide. Transistors made from these nanotubes have a much larger area through which charge carriers (electrons) can tunnel. Indeed, according to numerical simulations performed by the team, a 10 nm thin nanotube TFET with a 100 nm core gate boasts an output tunnelling current that is five times higher than that from GAA NW TFET of the same size.

“We believe that we can build the nanotube devices using conventional channel materials, such as silicon, silicon germanium, germanium and III-V materials,” he tells nanotechweb.org. “We can control the nanotube’s thickness down to less than 15 nm and control the gate length to make ultrashort channel devices.”

The epitaxial growth technique we employed to make the devices also allows for ultrasteep junctions for the source/channel/drain electrodes, he adds.

Outperforming gate-all-around NW FETs

The KAUST team used semi-classical transport numerical simulations to evaluate how different device architectures affect charge carrier transport behaviour. “We found that the nanotube FET design outperforms gate-all-around NW FETs thank to ‘lateral tunnelling’. The main band-to-band tunnelling mechanism for the devices strongly depends on the junction cross-sectional area, and since the nanotube in our heterostructure has a high available cross-section when compared to the nanowires in GAA devices, it thus has a higher normalized ON current,” explains team member Amir Hanna.

We also found that the “Shockley-Reed-Hall recombination”, or trap-assisted recombination, in the nanotube devices is lower that in GAA NW TFETs thanks to the higher current density within the indium arsenide source. Reducing such recombination helps increase the efficiency of a finished device.

Integrating devices into real-world circuits

The nanotube architecture described in this story was first developed by Hussain’s team back in 2011 and the researchers showed that it worked for silicon-based “over-the-barrier” devices as well as for all-silicon based TFETs. “This is our first attempt in evaluating a heterostructure material system made of nanotubes for a TFET application,” explains Hussain. “We have overcome the problem of increased power consumption in the devices as well as showing that we can control the ON current as a function of the core-gate diameter in the nanotube TFETs.”

It is not all plain sailing, however, and Hussain admits that integrating such devices into real-world circuits will be “complex”. “Another fundamental challenge we have to overcome is to form nearly ideal Ohmic contacts to these tiny nanotube and nanowire devices.”

The research is published in Scientific Reports doi:10.1038/srep09843.